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simplifying system integration tm 73 s8023c demo board user manual november 11 , 2009 rev. 1.3 um_ 8023c_027
73s8023c demo board user manual um_8023c_027 2 rev. 1.3 ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation i s a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the company?s warranty detailed in the teridian semiconductor corporation standard terms and conditions. the company assumes no responsibility for any errors which may appear in t his document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridi an.com
um_8023c_027 73s8023c demo board user manual rev. 1.3 3 table of contents 1 introduction ................................................................................................................................... 5 1.1 package contents .................................................................................................................... 5 1.2 safety and esd notes ............................................................................................................. 5 2 basic connections ........................................................................................................................ 6 3 hardware description .................................................................................................................... 7 3.1 demo board connectors, jumpers and test points ................................................................. 7 3.2 recommended operating conditions and absolute maximum ratings ..................................... 9 3.3 73s8023c pin description ....................................................................................................... 9 3.4 73s8023c pinout ................................................................................................................... 11 4 design considerations ................................................................................................................ 12 4.1 general layout rules ............................................................................................................ 12 4.2 optimization for compliance with emv and nds .................................................................... 12 5 73s8023c demo board schemati cs, pcb layouts and bill of materials .................................. 13 5.1 sch ematic .............................................................................................................................. 13 5.2 bill of materials ...................................................................................................................... 14 5.3 pcb layouts .......................................................................................................................... 15 6 ordering information ................................................................................................................... 18 7 related documentation ............................................................................................................... 18 8 contact information ..................................................................................................................... 18 revision history .................................................................................................................................. 19
73s8023c demo board user manual um_8023c_027 4 rev. 1.3 figure s figure 1: 73s8023c demo board ............................................................................................................ 5 figure 2: 73s8023c demo board basic connections .............................................................................. 6 figure 3: 73s8023c demo board connectors, jumpers and test points ................................................. 8 figure 4: 73s8023c 32qfn pinout (top view) ...................................................................................... 11 figure 5: 73s8023c demo board electrical schematic .......................................................................... 13 figure 6: 73s8023c demo board top view ........................................................................................... 15 figure 7: 73s8023c demo board bottom view ...................................................................................... 15 fi gure 8: 73s8023c demo board top signal layer ............................................................................... 16 figure 9: 73s8023c demo board middle layer 1, ground plane ........................................................... 16 figure 10: 73s8023 c middle layer 2, supply plane .............................................................................. 17 figure 11: 73s8023c demo board bottom signal layer ........................................................................ 17 table s table 1: 73s8023c demo board connector, jumper and test points ...................................................... 7 table 2: recommended operating conditions ......................................................................................... 9 table 3: absolute maximu m ratings ........................................................................................................ 9 table 4: 73s8023c card interface pins ................................................................................................... 9 table 5: 73s8023c miscellaneous pins ................................................................................................. 10 table 6: 73s8023c power and ground pins .......................................................................................... 10 table 7: 72s8023c microcontroller interface pins .................................................................................. 10 tab le 8: 73s8023c demo board bill of materials ................................................................................... 14 table 9: order numbers and packaging marks ...................................................................................... 18
um_8023c_027 73s8023c demo board user manual rev. 1.3 5 1 introduction the 73s8023c demo board is a platform for evaluating the teridian 73s8023c s mart c ard i nterface device . the board incorporates the 73s8023c integrated circuit and has been designed to operate either as a standalone platform (to be used in conjunction with an external microcontroller) or as a daughter card to be used in conjunction with the 73s1121f evaluation platform. the board has been designed to comply with the emv 2000 s pecification , version 4.0 . 73s8023c demo boards can easily be modified to comply with nds specifications by replacing a few external components that are highlighted in this document. figure 1 : 73s8023c demo board 1.1 package contents th e 73 s8023c demo board k it includes: ? a 73s8023c demo b oard ? the following documents on cd : ? 73s8023c data sheet ? 73s8023c demo b oard user manual (this document) ? application note 1.2 safety and esd notes connecting live voltages to the 73 s8023c demo board system will result in potentially hazardous voltages on the boards. extreme caution should be taken when handling the 73s8023c dem o board after connection to live voltages! the 73 s8023c demo board is esd sensitive! esd precautions should be taken when handling this board !
73s8023c demo board user manual um_8023c_027 6 rev. 1.3 2 basic connections the basic connections to the demo board are described below and shown in figure 2 . 1. connect p ower s upply: apply 3.3 v to pin 10 of j4. 2. control signals to the device can be connected through j2 and j4 (see figure 2 and the e lectrical s ch ematic , figure 5 ) . 3. to set the clock frequency with an external clock source : ? set jp1 to the sclk setting . ? apply clock source to pin 1 of j2 . ? apply 3.3v (1) or gnd (0) to clkdiv1 and clkdiv2 pins to set the desired clock rate as follows : ? clkdiv1 = clkdiv2 = 0 clock frequency = sclk/8 ? clkdiv1 = 0, clkdiv2 =1 clock frequency = sclk/4 ? clkdiv1 = 1, clkdiv2 =0 c lock frequency = sclk ? clkdiv1 = clkdiv2 = 1 clock frequency = sclk/2 4. to set the clock frequency using crystal y1 : ? the c rystal included on the demo board is 12 mhz . ? s et jp1 to xtal position . ? apply 3.3v (1) or gnd (0) to clkdiv1 and clkdiv2 pins to set the desired clock rate as follows: ? clkdiv1 = clkdiv2 = 0 clock frequency = 1.5 mhz ? clkdiv1 = 0, clkdiv2 =1 clock frequency = 3 mhz ? clkdiv1 = 1, clkdiv2 =0 clock frequen cy = 12 mhz ? clkdiv1 = clkdiv2 = 1 clock frequency = 6 mhz figure 2 : 73s8023c demo board basic connections
um_8023c_027 73s8023c demo board user manual rev. 1.3 7 3 hardware description 3.1 demo board connectors, jumpers and test points table 1 describes the 73s8023c demo board connectors, jumpers and test points. the item # in table 1 refer s to figure 3 . table 1 : 73s8023c demo board connector, jumper and test points item # schematic/ silkscreen reference name function connectors : 1 j2 auxiliary i nterface / 5v board power 73s8023c auxiliary interface (i/ouc, aux1uc, aux2uc), external clock (sclk) and interrupt ( off ) pins. the external clock (sclk) can be left open when jp1 is in position xtal. the 5v power supply is unused and must be left open and jp2 must be inserted in position 3.3v. 9 j4 3.3v board power / digital control signals 3.3v board power supply and the 73s8023c host control signals rstin, cmdvcc , 5v/ # v , pwrdw n, clkdiv2 and clkdiv1. 18 j5 smart card connector smart card connector. when inserting a card (credit card size format), contacts must face up. 11 j6 smart card connector sim/sam smart card format connecto r. j6 is wired in parallel to the smart card connector j5 (underneath the pcb). no sim/sam should be inserted when using the credit - card size connector j5. jumpers: 3 jp1 clock selection jumper to select between a crystal or an external clock as the f requency reference to the device. the default setting is for a crystal. 19 jp2 vpc select jumper to select the value of the power supply for the smart card dc - dc converter (73s8023c input vpc). to support both card voltages, jp2 must be set to position 3.3v. the default setting is 3.3v. 2 jp3 vdd select jumpe r to select the digital voltage which supplies the 73s8023c. must be set for 3.3v. 8 jp4 ? not used. 16 15 jp5 jp6 card polarity detect select the setting of jp5 and jp6 depends on the type of smart card connector used (nominally open or closed) and which 73s8023c card presence switch input is used. the switch is nominally open for the 73s8023c demo board. the jumpers can be set to: 1. use of pres (default): jp5 set to pres; jp6 set to vdd. 2. use of pres : jp5 set to preb; jp6 set to gnd. 13 jp7 clksel three pin header. set to vdd for sync operation. 17 jp8 cs three pin header. set to vdd for normal operation. 21 jp9 clkout two pin header. outputs the buffered version of xtalin. 22 jp10 strob e two pin header. controls clock signal when clksel=1.
73s8023c demo board user manual um_8023c_027 8 rev. 1.3 item # schematic/ silkscreen reference name function test points: 10 tp1 pin 18 * (vddf_adj) vdd voltage fault adjustment. the pin to the left is connected to the vddf_adj pin of the 73s8023c and the pin to the right is gnd. when either a resistor r3 , or a resistor network r1 and r3 is populated on the board, it adjusts the vdd fault level that internally triggers a card deactivation sequence. by default, the resistors r1 and r3 are not connected. this provides a vdd fault level of 2.3v typical (in ternally set to the 73s8023c). ref er to the 73s8023c data s heet for further information about vdd fault level and determination of the resistor values. * the silkscreen is in error. it is shown a s ?pin 18? when actually it is p in 17. 20 tp2 factory tes t factory test pin. do not connect. 7 12 6 14 5 4 tp 3 tp 4 tp 5 tp 6 tp7 tp8 vcc i/o rst c8 clk c4 2 - pin test points for each respective smart card signal. the pin label name is the respective signal (i.e. vcc, clk) and the 2nd pin is gnd. figure 3 : 73s8023c demo board connectors, jumpers and test points
um_8023c_027 73s8023c demo board user manual rev. 1.3 9 3.2 recommended operating conditions and absolute maximum ratings table 2 lists the recommended operating conditions and table 3 lists the absolute maximum ratings. operation outside these rating limits may cause permanent damage to the device. table 2 : recommended operating conditions parameter rating supply voltage v dd 2.7 to 3.6 vdc supply voltage v pc 2.7 to 3.6 vdc ambient operating temperature - 40 c to +85 c input voltage for digital inputs 0 v to v dd + 0.3 v table 3 : absolute maximum ratings parameter rating supply voltage v dd - 0.5 to 4. 0 vdc supply voltage v pc - 0.5 to 4.0 vdc input voltage for digital inputs - 0.3 to (vdd+0.5) vdc storage temperature - 60 c to 150 c pin voltage - 0.3 to (vdd+0.5) vdc pin current 100 ma esd tolerance ? card interface pins +/ - 6 kv esd tolerance ? o ther pins +/ - 2 kv esd testing on card pins is hbm condition, 3 pulses, each polarity referenced to ground. 3.3 73s8023c pin description table 4 : 73s8023c card interface pins name pin # description i/o 9 card i/o: data signal to/fro m card. includes a pull - up resistor to v cc. aux1 11 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 10 aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 14 card reset: provides reset (rst) signal to card. clk 13 card clock: provides clock signal (clk) to card. the rate of this clock is determined by crystal oscillator frequency or external clock input and clkdiv selections. pres 7 card presence switch: active high indicates card is present. should be tie d to gnd when not used, but it i ncludes a high - impedance pull - down resistor. pres 6 card presence switch: active low indicates card is present. should be tied to v dd when not used, but it i ncludes a high - impedance pull - up resistor. vcc 15 card power supply: lo gically controlled by sequencer output of ldo regulator. requires an external filter capacitor to the card gnd. gnd 12 card ground .
73s8023c demo board user manual um_8023c_027 10 rev. 1.3 table 5 : 73s8023c miscellaneous pins name pin # description xtali n 23 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. xtalout 24 crystal oscillator output: connected to crystal. left open if xtalin is being used as external clock input. vddf_adj 17 v dd fault thre shold adjustment input: this pin can be used to adjust the v ddf values (controls deactivation of the card) . must be left open if unused. nc 4 non - connected pin. table 6 : 73s8023c power and ground pins name pin # description vdd 20 system interface supply voltage and supply voltage for internal circuitry. vpc 3 dc- dc converter power supply source. gnd 1 dc- dc converter ground. gnd 21 digital ground. lin 2 external inductor. connect external inductor from pin 2 to vpc. keep the inductor close to pin 2. table 7 : 72s8023c microcontroller interface pins name pin # description cmdvcc 18 command vcc (negative assertion): logic low on this pin causes the ldo regulator to ramp the v cc supply to the card a nd initiates a card activation sequence, if a card is present. 5v/ #v 31 5 volt / 3 volt card selection: logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation. when the part is to be used with a single card voltage, this pin should be tied to either gnd or v dd . however, it includes a high impedance pull - up resistor to default this pin high (selection of 5v card) when not connected. pwrdn 5 power down control input. active h igh. when the power down mode is set high, al l internal analog functions are disabled to place the 73s8023c in its lowest power consumption mode. the power down mode is only allowed out of a card session (i.e. when cmdvcc = 1) clkdiv1 clkdiv2 29 30 sets the divide ratio from the xtal oscillator (or external clock input) to the card clock. these pins include pull - down resistors. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 22 interrupt signal to the processor. active l ow - m ulti - function indicating fa ult conditions and/or card presence. open drain output configuration; includes an internal 22 k pull - up to v dd. rstin 19 reset input: this signal is the reset command to the card. i/ouc 26 system controller data i/o to/from the card. includes a pull - u p resistor to v dd. aux1uc 27 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd.
um_8023c_027 73s8023c demo board user manual rev. 1.3 11 name pin # description aux2uc 28 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd. clksel 16 selects clk and rst operational mode. when clksel is low (default), the circuit is configured for asynchronous card operation and the control of clk and rst is managed by the sequencer. when clksel is high, the clk signal is a buffered copy of strobe and the rst signal is d irectly controlled by rstin. clkout 32 clkout is a buffered version of the signal on pin xtalin. strobe 25 when clksel = 1, the signal clk is controlled directly by strobe. cs 8 when cs = 1, the control and signal pins are configured normally. when c s is set low, cmdvccb , rstin, 5v/3v, clkdiv1, clkdiv2, clksel, and strobe are latched. i/ouc, aux1uc, and aux2uc are set to high - impedance pull - up mode (3 a pull - up to vdd) and do not pass data to or from the smart card. 3.4 73s8023c pinout 6 7 8 9 5 4 3 2 1 17 18 19 20 24 23 22 21 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 gnd lin vpc nc prdwn pres pres cs xtalout xtalin off gnd vdd rstin cmdvcc vddf _ adj i / o a u x 2 a u x 1 g n d c l k r s t v c c c l k s e l 73s 8023 c s t r o b e c l k o u t 5 v / # v c l k d i v 2 c l k d i v 1 a u x 2 u c a u x 1 u c i / o u c figure 4 : 73s8023c 32qfn pinout (top view)
73s8023c demo board user manual um_8023c_027 12 rev. 1.3 4 design considerations 4.1 general layout rules ? route the auxiliary signals away from card interface signals . ? keep the clk signal as short as possible and with few bends in the trace. keep the route of the clk trace to one layer (avoid vias to other plane). keep the clk trace away from other traces , especially rst and vcc. filtering of the clk trace is allowed for noise purpose. up to 30 pf to ground is allowed at the clk pin of the smart card connector. in addition, t he zero ohm series resistor, r7, can be replaced for additional filtering (no more than 100 ). ? keep the vcc trace as short as possible. make the trace a minimum of 0.5 mm thick. in addition, keep the vcc away from other traces , especially rst and clk. ? keep the trace from l1 to pin 2 of the ic as short as possible. ? keep the rst trace away from the vcc and clk traces. up to 30 pf to ground is allowed for filtering . ? keep the 0.1 f capacitor close to the vdd pin of the device and directly take the other end to ground . ? keep the 0.1 f capacitor close to the vpc pin of the device and directly take the other end to ground . ? keep the 3.3 f (1.0 f for nds) capacitor close to the vcc pin of the smart card connecto r and directly take other end to ground . 4.2 optimization for compliance with emv and nds the default configuration of the d emo board contains a 27 pf capacitor (c12) from the clk pin of the smart connector to ground and a 27 pf capacitor (c13) from the rst pin of the smart connector to ground. these capacitors serve as filters for the clk and rst signals in the case of long traces or test equipment perturbations. the capacitor on clk reduces ringing on the trace, reduces coupling to other traces and slows down the edge of the clk signal. the capacitor on rst helps the perturbation specification in a noisy environment. the filter capacitors can be useful in the emv test environment and have no effect on nds testing . c12 and c13 are represented on both the schematic and the bom. these capacitors are optional filter capacitors on the smart card lines clk and rst, respectively for each card interface. these cap acitors may be adjusted (value not to exceed 30 pf) or removed to optimize performance in each spe cific application (pcb, card clock frequency, compliance with applicable standards etc). the default vcc capacitor of 3.3 f is required to meet the dynamic vcc (smart card supply) transient current requirement as specified in the emv2000 version 4.0 spec ification. for compliance with nds, a smaller capacitor of 1 f is required to meet the activation discharge time specification.
um_8023c_027 73s8023c demo board user manual rev. 1.2 13 5 73 s8023c demo board schematic s, pcb layouts and bill of materials 5.1 schematic r8 ru signal names refer to 73s1121f evaluation board sio jp1 1 2 3 usr4 5v connectors are positioned to allow multiple 8023c boards (stackin) to a 73s1121f evaluation board. also used for connectiong external signals when usedas a stand alone board usr3 usr2 j5 smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 j4 tsm_110_01_l_sv 1 2 3 4 5 6 7 8 9 10 jp2 1 2 3 resistors are not populated 3.3v c9 card detect polarity select r1 clkdiv2 5v 5v jp4 header lock 3 1 2 3 tp1 1 2 sclk +5v sclk do not populate tp2 gnd r10 ru vdd gnd j3 ssm_110_l_sv 1 2 3 4 5 6 7 8 9 10 10uh r5 usr1 tp3 1 2 vdd select r12 rd r13 rd sc8 rst c12 27pf + c1 10uf vcc resistors are not populated c11 3.3uf vdd tp4 1 2 vddf_adj xtalin select keep clk trace away from rst and i/o trace resistors are not populated r4 0 +3.3v j6 sim/sam connector 1 2 3 4 5 6 7 8 c1 c2 c3 c5 c6 c7 sw1 sw2 test must select 3.3v signal names refer to 73s1121f evaluation board r2 0 sclk s_c4 u2 73s8023c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gnd lin vpc nc prdwn pres pres cs i/o aux2 aux1 gnd clk rst vcc clksel vddf_adj cmdvcc rstin vdd gnd off xta l i n xtalout strobe i/ouc aux1uc aux2uc clkdiv1 clkdiv2 5v/3v clkout rstin 3.3v usr5 y1 12.000mhz 1 4 + c10 10uf clk r9 ru c2 0.1uf tp2 1 2 int2 usr7 jp9 clkout 1 2 vdd 5.0v clkdiv1 c13 27pf 3.3v tp3 to tp8 to be placed very close to the pads of j5 5v3vb sio vdd 5.0v tp7 1 2 i/o card detection switches are nornally open must select 3.3v c4 3.3v jp6 1 2 3 c5 22pf pres usr6 r6 jumper must select vdd gnd c8 0.1uf r11 rd vpc select offb j1 ssm_110_l_sv 1 2 3 4 5 6 7 8 9 10 jp10 strobe 1 2 jumper must select pres vdd vdd tp8 1 2 cmdvccb pres gnd tp6 1 2 sc4 3.3v pgnd tp5 1 2 5.0v gnd prdwn gnd c8 s_c8 c4 22pf r14 +5v r3 jp8 cs 1 2 3 jp7 clksel 1 2 3 l1 gnd + c3 10uf j2 tsm_110_01_l_sv 1 2 3 4 5 6 7 8 9 10 xtal vdd usr0 jp5 1 2 3 jp3 1 2 3 r7 0 figure 5 : 73 s8023c dem o board electrical schematic
73s8023c demo board user manual um_8023c_027 14 rev. 1.2 5.2 bill of materials table 8 provides the bill of materials for the 73s8023c demo board schematic provided in figure 5 . table 8 : 73s8023c demo board bil l of materials item quantity reference part pcb footprint digikey p art n umber part n umber manufacturer 1 3 c1,c3,c10 10 f 805 pcc2225ct - nd ecj - 2fb0j106m panasonic 2 2 c2,c8 0.1 f 603 pcc1762ct - nd ecj - 1vb1c104k panasonic 3 2 c4,c5 22 pf 603 pcc220acvct - nd ecj - 1vc1h220j panasonic 4 1 c9 x 603 x x not populated 5 1 c11 3.3 f 805 pcc1925ct - nd ecj - 2yb0j335k panasonic 6 2 c12, c13 27 pf 402 pcc270cqct - nd ecj - 0ec1h270j panasonic 7 7 jp1,jp2,jp3,jp5, jp6,jp7,jp8 header 3 3pins, 2.54 mm pi t ch s1011 - 36 - nd p zc36saan sullins 8 1 jp4 x 3pins, 2.54 mm pi t ch x x not populated 9 2 jp9,jp10 header 2 2x1_header s1011 - 36 - nd pzc36saan sullins 10 2 j1,j3 ssm_110_l_sv ssm_110_l_sv x ssm_110_l_sv samtec 11 2 j2,j4 tsm_110_01_l_sv tsm_110_01_l_sv x tsm_110_01_l_sv sam tec 12 1 j5 smart card connector itt_ccm02 - 2504 ccm02 - 2504 - nd ccm02 - 2504 ittcannon 13 1 j6 sim/sam connector itt_ccm03 - 3754 ccm03 - 3754ct - nd ccm03 - 3754 ittcannon 14 1 l1 10 h 445 - 1186 - 1 - nd slf7032t - 100m1r4 - 2 tdk 15 3 r2,r4,r7 0 603 p0.0gct - nd erj - 3ge y0r00v panasonic 16 6 r1,r5,r6,r8,r9,r10 ru 1 603 x x 17 4 r3,r11,r12,r13 rd 1 603 x x 18 7 tp1,tp3,tp4,tp5, tp6,tp7,tp8 tp 2x1_header s1011 - 36 - nd pzc36saan sullins 19 1 u2 73s802 3 c 32qfn x 73s802 3 c teridian semiconductor 20 1 y1 12.000 mhz hc- 49us x190 - nd ecs - 120 - 20- 4dn ecs 1 ru and rd are not populated on the board. they can be implemented to adjust the features of the smart card reader.
um _8023c_027 73s8023c demo board user manual rev. 1.3 15 5.3 pcb layout s figure 6 : 73 s8023c demo board top view figure 7 : 73 s8023c demo board bottom view
73s8023c demo board user manual um_8023c_027 16 rev. 1.3 figure 8 : 73 s8023c demo board top signal layer figure 9 : 73 s8023c demo board middle layer 1, ground plane
um _8023c_027 73s8023c demo board user manual rev. 1.3 17 figure 10 : 73s8023c mi ddle layer 2, supply plane figure 11 : 73s8023c demo board bottom signal layer
73s8023c demo board user manual um_8023c_027 18 rev. 1.3 6 ordering information table 9 lists the order number used to identify the 73 s8023c demo board . table 9 : order number part description order number 73s8023c 32 - pin qfn demo board 73s8023c - db 7 related documentation the following 73 s8023c documents are available from teridian semiconductor corporation: 73 s8023c data sheet 73s8023c demo board user manu al (this document) 8 contact information for more information about teridian semiconductor products or to che ck the availability of the 73 s8023c , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr .support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com .
um _8023c_027 73s8023c demo board user manual rev. 1.3 19 revision history revision date description 1.0 8 / 3 /200 4 first publication . 1.1 11/ 26/20 04 minor co rrections . 1.2 8/23/2005 added new logo. 1.3 11/11 /2009 added section 1.1, package contents. added section 1.2, safety and esd notes. added section 6, ordering information. added section 7, related documentation. added section 8, contact information. mis cellaneous editorial changes.

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